1. Field of the Invention
The invention relates generally to lithography methods and lithography structures for fabricating microelectronic structures. More particularly, the invention relates to enhanced performance lithography methods and lithography structures for fabricating microelectronic structures.
2. Description of the Related Art
Microelectronic structures, and in particular semiconductor structures, are fabricated using lithographic methods. Lithographic methods typically include the use of successive resist layers that are latently imaged and subsequently developed and patterned over a substrate, such as but not limited to a semiconductor substrate, for purposes of fabricating any of several structures within the substrate. Particular structures that may be fabricated within a semiconductor substrate while using a patterned resist layer include: (1) selectively deposited structures; and (2) selectively etched structures; as well as (3) selectively ion implanted structures. Particular additional structures that may be fabricated with respect to a semiconductor substrate include semiconductor device related structures and contact structures connected thereto, as well as multilayer dielectric and metallization (i.e., via and interconnect) structures.
The use of lithographic methods when fabricating microelectronic structures is certain to continue as microelectronic fabrication technology advances. However, as microelectronic structure and device dimensions decrease and microelectronic integration levels increase, performance requirements of lithographic methods that are used for fabricating microelectronic structures also generally increase.
Various lithographic methods and lithographic structures that are used for fabricating microelectronic structures are known within the microelectronic fabrication art. For example, Lin, in U.S. Pat. No. 6,875,624, teaches a lithographic method for efficiently and effectively fabricating a semiconductor structure. This particular lithographic method uses an electron beam lithography method for fabricating critically dimensioned semiconductor structures located within a semiconductor substrate, and an optical lithography method for fabricating non-critically dimensioned semiconductor structures located within the semiconductor substrate.
In addition, Smith et al., in U.S. Pat. No. 7,160,657, teaches a particular method for calibrating a lithographic exposure apparatus that may be used for fabricating a semiconductor structure. The particular method uses a reference reticle that includes a two-dimensional array of otherwise standard alignment attributes.
Microelectronic structure and device dimensions, including in particular semiconductor structure and device dimensions, are certain to continue to decrease as microelectronic technology advances. To that end, desirable are advanced lithographic methods and structures that efficiently facilitate continued microelectronic structure and microelectronic device scaling.